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64-macrocell max? epld cy7c343b cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 document #: 38-03038 rev. ** revised december 8, 1999 43b features ? 64 max macrocells in 4 labs 8 dedicated inputs, 24 bidirectional i/o pins programmable interconnect array advanced 0.65-micron cmos technology to increase performance available in 44-pin hlcc, plcc lowest power max device functional description the cy7c343b is a high-performance, high-density erasable programmable logic device, available in 44-pin plcc and hlcc packages. the cy7c343b contains 64 highly flexible macrocells and 128 expander product terms. these resources are divided into four logic array blocks (labs) connected through the program- mable inter-connect array (pia). there are 8 input pins, one that doubles as a clock pin when needed. the cy7c343b also has 28 i/o pins, each connected to a macrocell (6 for labs a and c, and 8 for labs b and d). the remaining 36 macrocells are used for embedded logic. the cy7c343b is excellent for a wide range of both synchro- nous and asynchronous applications. max is a registered trademark of altera corporation. macrocell 17 macrocell 18 macrocell 19 macrocell 20 macrocell 21 macrocell 22 macrocell 23 macrocell 24 macrocell 38 macrocell 37 macrocell 36 macrocell 35 macrocell 34 macrocell 33 9input 11 input 12 input 13 input p i a macrocell 1 macrocell 2 macrocell 3 macrocell 4 macrocell 5 macrocell 6 macrocell 56 macrocell 55 macrocell 54 macrocell 53 macrocell 52 macrocell 51 macrocell 50 macrocell 49 macrocells 7 - 16 macrocells57 - 64 macrocells 25 - 32 macrocells39 - 48 input 35 input/clk 34 input 33 input 31 2 4 5 6 7 8 1 44 42 41 40 39 38 37 30 29 28 27 26 24 system clock (3, 14, 25, 36) (10, 21, 32, 43) v cc gnd lab a lab b lab d lab c c343b-1 logic block diagram dedicated inputs i/o pins 15 16 17 18 19 20 22 23 i/o pins i/o pins i/o pins
cy7c343b document #: 38-03038 rev. ** page 2 of 12 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature .................................. ? 65 c to+135 c ambient temperature with power applied.............................................. ? 65 c to+135 c maximum junction temperature (under bias)................................................................. 150 c supply voltage to ground potential [1] ............. ? 2.0v to+7.0v dc output current, per pin [1] ................... ? 25 ma to +25 ma dc input voltage [1] ......................................... ? 2.0v to +7.0v note: 1. minimum dc input is ? 0.3v. during transactions, the inputs may undershoot to ? 2.0v or overshoot to 7.0v for input currents less then 100 ma and periods shorter than 20 ns. pin configuration selection guide 7c343b-25 7c343b-30 7c343b-35 maximum access time (ns) 25 30 35 i/o 4 53 10 11 9 8 7 36 35 37 38 39 19 18 20 12 13 34 33 21 21 22 hlcc, plcc top view 17 16 15 14 23 24 26 25 27 28 29 30 31 32 44 43 41 42 40 v cc gnd i/o i/o i/o v cc input input/clk input gnd input i/o i/o v cc gnd i/o c343b-2 6 7c343 i/o i/o i/o i/o i/o i/o i/o i/o input gnd v cc input input input i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o operating range range ambient temperature v cc commercial 0 c to +70 c 5v 5% industrial ? 40 c to +85 c 5v 10% military ? 55 c to +125 c (case) 5v 10%
cy7c343b document #: 38-03038 rev. ** page 3 of 12 electrical characteristics over the operating range parameter description test conditions min. max. unit v cc supply voltage maximum v cc rise time is 10 ms 4.75(4.5) 5.25(5.5) v v oh output high voltage i oh = ? 4.0 ma dc [2] 2.4 v v ol output low voltage i ol = 8 ma dc [2] 0.45 v v ih input high level 2.0 v cc +0.3 v v il input low level ? 0.3 0.8 v i ix input current v i = v cc or ground ? 10 +10 a i oz output leakage current v o = v cc or ground ? 40 +40 a t r recommended input rise time 100 ns t f recommended input fall time 100 ns capacitance parameter description test conditions max. unit c in input capacitance v in = 0v, f = 1.0 mhz 10 pf c out output capacitance v out = 0v, f = 1.0 mhz 20 pf note: 2. the i oh parameter refers to high-level ttl output current; the i ol parameter refers to low-level ttl output current. ac test loads and waveforms 3.0v 5v output r1 464 ? r2 250 ? 50 pf including jig and scope gnd 90% 10% 90% 10% < 6 ns 5v output r1 464 ? r2 250 ? 5pf including jig and scope (a) (b) output 1.75v equivalent to: th venin equivalent (commercial/military) all input pulses c343b-4 c343b-5 163 ? < 6 ns
cy7c343b document #: 38-03038 rev. ** page 4 of 12 programmable interconnect array the programmable interconnect array (pia) solves intercon- nect limitations by routing only the signals needed by each logic array block. the inputs to the pia are the outputs of every macrocell within the device and the i/o pin feedback of every pin on the device. unlike masked or programmable gate arrays, which induce variable delay dependent on routing, the pia has a fixed delay. this eliminates undesired skews among logic signals, which may cause glitches in internal or external logic. the fixed de- lay, regardless of programmable interconnect array configura- tion, simplifies design by ensuring that internal signal skews or races are avoided. the result is simpler design implementa- tion, often in a single pass, without the multiple internal logic placement and routing iterations required for a programmable gate array to achieve design timing objectives. design recommendations operation of the devices described herein with conditions above those listed under ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sec- tions of this data sheet is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. the cy7c343b contains circuitry to protect device pins from high static voltages or electric fields; however, normal precautions should be taken to avoid apply- ing any voltage higher than maximum rated voltages. for proper operation, input and output pins must be con- strained to the range gnd < (v in or v out ) < v cc . unused inputs must always be tied to an appropriate logic level (either v cc or gnd). each set of v cc and gnd pins must be con- nected together directly at the device. power supply decou- pling capacitors of at least 0.2 f must be connected between v cc and gnd. for the most effective decoupling, each v cc pin should be separately decoupled to gnd, directly at the device. decoupling capacitors should have good frequency response, such as monolithic ceramic types. timing considerations unless otherwise stated, propagation delays do not include expanders. when using expanders, add the maximum ex- pander delay t exp to the overall delay. similarly, there is an additional t pia delay for an input from an i/o pin when com- pared to a signal from a straight input pin. when calculating synchronous frequencies, use t s1 if all inputs are on the input pins. when expander logic is used in the data path, add the appropriate maximum expander delay, t exp to t s1 . determine which of 1/(t wh + t wl ), 1/t co1 , or 1/(t exp + t s1 ) is the lowest frequency. the lowest of these frequencies is the maximum data path frequency for the synchronous configura- tion. typical i cc vs. f max output drive current when calculating external asynchronous frequencies, use t as1 if all inputs are on dedicated input pins. when expander logic is used in the data path, add the appro- priate maximum expander delay, t exp to t as1 . determine which of 1/(t awh + t awl ), 1/t aco1 , or 1/(t exp + t as1 ) is the low- est frequency. the lowest of these frequencies is the maxi- mum data path frequency for the asynchronous configuration. the parameter t oh indicates the system compatibility of this device when driving other synchronous logic with positive in- put hold times, which is controlled by the same synchronous clock. if t oh is greater than the minimum required input hold time of the subsequent synchronous logic, then the devices are guaranteed to function properly with a common synchro- nous clock under worst-case environmental and supply volt- age conditions. 200 150 100 50 1 khz 10 khz 100 khz 1 mhz i cc maximum frequency 10 mhz 0 50 mhz 100 hz active (ma) typ. v cc = 5.0v room temp. c343b ? 7 01 2 3 4 i output current (ma) typical v o output voltage (v) 250 200 150 100 50 5 o i oh i ol v cc = 5.0v room temp. c343b ? 8
cy7c343b document #: 38-03038 rev. ** page 5 of 12 figure 1. cy7c343b internal timing model external synchronous switching characteristics over operating range parameter description 7c343b-25 7c343b-30 7c343b-35 unit min. max. min. max. min. max. t pd1 dedicated input to combinatorial output delay [3] com ? l/ind 25 30 35 ns t pd2 i/o input to combinatorial output delay [3] com ? l/ind 40 45 55 ns t su global clock setup time com ? l/ ind 15 20 25 ns t co1 synchronous clock input to output delay [3] com ? l/ind 14 16 20 ns t h input hold time from synchronous clock input com ? l/ind 0 0 0 ns t wh synchronous clock input high time com ? l/ind 8 10 12.5 ns t wl synchronous clock input low time com ? l/ind 8 10 12.5 ns f max maximum register toggle frequency [4] com ? l/ind 62.5 50 40 mh z t cnt minimum global clock period com ? l/ind 20 25 30 ns t odh output data hold time after clock com ? l/ind 2 2 2 ns f cnt maximum internal global clock frequency [5] com ? l/ind 50 40 33.3 mh z notes: 3. c1 = 35 pf. 4. the f max values represent the highest frequency for pipeline data. 5. this parameter is measured with a 16-bit counter programmed into each lab. logic array control delay t lac expander delay t exp clock delay t ic t rd t comb t latch input delay t in pia delay t pia register output delay t od t xz t zx logic array delay t lad feedback delay t fd i/o delay t io input/ output input c343b-9 system clock delay t ics t rh t rsu t pre t clr
cy7c343b document #: 38-03038 rev. ** page 6 of 12 external asynchronous switching characteristics over operating range parameter description 7c343b-25 7c343b-30 7c343b-35 unit min. max. min. max. min. max. t aco1 asynchronous clock input to output delay [3] com ? l/ind 25 30 35 ns t as1 dedicated input or feedback set-up time to asynchronous clock input com ? l/ind 5 6 8ns t ah input hold time from asynchronous clock input com ? l/ind 6 8 10 ns t awh asynchronous clock input high time [6] com ? l/ind 11 14 16 ns t awl asynchronous clock input low time [6] com ? l/ind 9 11 14 ns t acnt minimum internal array clock frequency com ? l/ind 20 25 30 ns f acnt maximum internal array clock frequency [5] com ? l/ind 50 40 33.3 mhz internal switching characteristics over operating range parameter description 7c343b-25 7c343b-30 7c343b-35 min. max. min. max. min. max. unit t in dedicated input pad and buffer delay com ? l/ind 5 7 11 ns t io i/o input pad and buffer delay com ? l/ind 6 6 11 ns t exp expander array delay com ? l/ind 12 14 20 ns t lad logic array data delay com ? l/ind 12 14 14 ns t lac logic array control delay com ? l/ind 10 12 13 ns t od output buffer and pad delay [3] com ? l/ind 5 5 6 ns t zx output buffer enable delay [3] com ? l/ind 10 11 13 ns t xz output buffer disable delay [7] com ? l/ind 10 11 13 ns t rsu register set-up time relative to clock signal at register com ? l/ind 6 8 12 ns t rh register hold time relative to clock signal at register com ? l/ind 4 6 8 ns t latch flow-through latch delay com ? l/ind 3 4 4 ns t rd register delay com ? l/ind 1 2 2 ns t comb transparent mode delay com ? l/ind 3 4 4 ns t ic asynchronous clock logic delay com ? l/ind 14 16 18 ns t ics synchronous clock delay com ? l/ind 3 2 1 ns t fd feedback delay com ? l/ind 1 1 2 ns t pre asynchronous register preset time com ? l/ind 5 6 7 ns t clr asynchronous register clear time com ? l/ind 5 6 7 ns t pia programmable interconnect array delay time com ? l/ind141620ns notes: 6. this parameter is measured with a positive-edge-triggered clock at the register. for negative-edge clocking, the t ach and t acl parameter must be swapped. 7. c1 = 5 pf.
cy7c343b document #: 38-03038 rev. ** page 7 of 12 switching waveforms c343b-10 t xz t zx t od high impedance state clock from logic array logic array data from output pin t rd internal synchronous internal asynchronous t io t awh t awl t f t in t ic t su t rh t rd ,t latch t fd t clr ,t pre t fd clock pin logic array logic array clock from data from clock into logic array register output to another lab t pia to local lab register output logic array c343b-11 t r t in t ics t rsu t rh c343b-12 internal synchronous system clock pin system clock at register data from logic array
cy7c343b document #: 38-03038 rev. ** page 8 of 12 switching waveforms (continued) internal combinatorial t in t exp t lac ,t lad c343b-13 t comb t od input pin i/o pin logic array logic array output input array delay expander output pin t io external combinatorial dedicated input/ i/o input combinatorial output c343b-14 t pd1 /t pd2 c343b-15 t wl t su t h logic array t wh external synchronous clock at register synchronous synchronous logic array data from registered clock pin outputs t co1
cy7c343b document #: 38-03038 rev. ** page 9 of 12 ordering information speed (ns) ordering code package name package type operating range 25 cy7c343b-25hc/hi h67 44-pin windowed leaded chip carrier commercial/industrial cy7c343b-25jc/ji j67 44-lead plastic leaded chip carrier 30 cy7c343b-30jc/ji j67 44-lead plastic leaded chip carrier commercial/industrial 35 cy7c343b-35hc/hi h67 44-pin windowed leaded chip carrier commercial/industrial cy7c343b-35jc/ji j67 44-lead plastic leaded chip carrier switching waveforms (continued) external asynchronous t ah t as1 t awh t awl dedicated inputs or registered feedback c343b-16 asynchronous clock input
cy7c343b document #: 38-03038 rev. ** page 10 of 12 package diagrams 44-pin windowed leaded chip carrier h67 51-80079
cy7c343b document #: 38-03038 rev. ** page 11 of 12 ? cypress semiconductor corporation, 1999. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagrams (continued) 44-lead plastic leaded chip carrier j67 51-85003-a
cy7c343b document #: 38-03038 rev. ** page 12 of 12 document title: cy7c343b 64-macrocell max ? epld document number: 38-03038 rev. ecn no. issue date orig. of change description of change ** 106461 07/11/01 szv change from spec number: 38-00862 to 38-03038

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